TSMC's 2nm N2 process officially enters volume production

Fabrication starts at the Kaohsiung plant with expansion to a second site in 2026

Serving tech enthusiasts for over 25 years.
TechSpot means tech analysis and advice you can trust.

What just happened? TSMC has begun volume production of chips based on its N2 process technology, marking a major new step in 2nm-class node manufacturing. The company disclosed the milestone on its website rather than through a formal press announcement, fulfilling its goal to begin production in the fourth quarter of 2025.

A statement on the company's 2nm technology page confirms that volume production began in 4Q25 as planned.

The N2 node represents a significant architectural shift for TSMC. It is the company's first implementation of gate-all-around (GAA) nanosheet transistors – an advancement beyond the FinFET design used in earlier generations.

In a GAA layout, the transistor's gate completely encloses the channel formed by stacked horizontal nanosheets, enabling tighter electrostatic control and reducing current leakage. This approach allows for smaller, more efficient transistors without loss of performance.

Alongside GAA, N2 introduces super-high-performance metal-insulator-metal capacitors (SHPMIM) within the power delivery network. TSMC says these capacitors provide more than twice the capacitance density of the company's earlier SHDMIM design while cutting both sheet resistance and via resistance in half. Those reductions improve power stability and overall energy efficiency across the chip.

Compared with the company's N3E node, N2 offers an expected performance gain of 10% to 15% at the same power level, or a 25% to 30% power reduction to achieve equivalent performance. Transistor density increases about 15% for mixed designs that include logic, analog, and SRAM circuits. Logic-only layouts can see as much as a 20% jump in density.

TSMC began manufacturing N2 chips at its new Fab 22 facility near Kaohsiung, in southern Taiwan. Earlier expectations had pointed to Fab 20, located near Hsinchu and adjacent to TSMC's global R&D center, as the likely starting point for the new process. Fab 20 is now expected to begin mass production later.

// Related Stories

• Intel could return to Macs and iPads by 2027, but this time as Apple's contract chipmaker
• Asus denies recent reports of launching its own memory chip facility

Starting production at Kaohsiung marks a change in the company's usual ramp strategy. TSMC typically introduces new process nodes with smaller mobile chips before expanding to high-performance computing products. This rollout includes both categories, covering designs for smartphones as well as AI and HPC chips.

During an earnings call in October, TSMC chief executive C.C. Wei said that "N2 is well on track for volume production later this quarter, with good yield," and that the company expects "a faster ramp in 2026, fueled by both smartphone and HPC AI applications."

Demand from multiple customers has led TSMC to prepare both N2-capable fabs simultaneously. The company plans to expand capacity across these facilities through 2026 to accommodate production of two derivative technologies: N2P and A16.

"With our strategy of continuous enhancements, we will also introduce N2P as an extension of our N2 family," Wei said. "N2P features further performance and power benefits on top of N2 and volume production scheduled for second half 2026. We also introduced A16 featuring our best-in-class Super Power Rail, or SPR. A16 is best suited for specific HPC products with complex signal routes and dense power delivery networks. Volume production is on track for second half 2026."

The N2P variant is a performance-enhanced evolution of the base process, while A16 integrates Super Power Rail backside power delivery, a feature designed to improve power efficiency and routing density for large AI and HPC processors. Both will begin manufacturing in the latter half of 2026, continuing TSMC's two-year cadence of introducing higher-performance process extensions.